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FEATURES Single and Dual 2-to-1 Also Available (AD8180 and AD8182) Fully Buffered Inputs and Outputs Fast Channel Switching: 10 ns High Speed > 700 MHz Bandwidth (-3 dB) > 750 V/ s Slew Rate Fast Settling Time of 15 ns to 0.1% Excellent Video Specifications (RL > 2 k ) Gain Flatness of 0.1 dB of 75 MHz 0.01% Differential Gain Error, RL = 10 k 0.01 Differential Phase Error, RL = 10 k Low Power: 4.4 mA Low Glitch: < 25 mV Low All-Hostile Crosstalk of -95 dB @ 5 MHz High "OFF" Isolation of -115 dB @ 5 MHz Low Cost Fast Output Disable Feature for Connecting Multiple Devices APPLICATIONS Pin Compatible with HA4314* and GX4314* Video Switchers and Routers Pixel Switching for "Picture-In-Picture" Switching in LCD and Plasma Displays
700 MHz, 5 mA 4-to-1 Video Multiplexer AD8184
FUNCTIONAL BLOCK DIAGRAM
IN0 1 GND 2 IN1 3 GND 4 IN2 5 GND 6 IN3 7 +1 +1
DECODER
+1
14 +VS 13 A0 12 A1 11 ENABLE 10 OUT 9 NC
+1
AD8184
8 -VS
NC = NO CONNECT
Table I. Truth Table
ENABLE 0 0 0 0 1 A1 0 0 1 1 X A0 0 1 0 1 X OUTPUT IN0 IN1 IN2 IN3 High Z
PRODUCT DESCRIPTION
NORMALIZED OUTPUT - dB
The AD8184 is a high speed 4-to-1 multiplexer. It offers -3 dB signal bandwidth of 700 MHz along with a slew rate of 750 V/s. With 95 dB of crosstalk and 115 dB isolation, it is useful in many high speed applications. The differential gain and differential phase error of 0.01% and 0.01, along with 0.1 dB flatness of 75 MHz, make AD8184 ideal for professional video multiplexing. It offers 10 ns switching time, making it an excellent choice for pixel switching (picture-in-picture) while consuming less than 4.5 mA on 5 V supply voltage. The AD8184 offers a high speed disable feature allowing the output to be put into a high impedance state. This allows multiple outputs to be connected together for cascading stages while the "OFF" channels do not load the output bus. It operates on voltage supplies of 5 V and is offered in 14-lead PDIP and SOIC packages.
*All trademarks are the property of their respective holders.
5 4 3 2 1 0 -1 -2 -3 -4 -5 1M 10M 100M FREQUENCY - Hz 1G VIN = 50mVrms RL = 5k
Figure 1. Small Signal Frequency Response
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
AD8184-SPECIFICATIONS (@ T = +25 C, V =
A S
5 V, RL = 2 k
unless otherwise noted)
AD8184A
Min Typ Max Units
Parameter SWITCHING CHARACTERISTICS Channel Switching Time1 50% Logic to 10% Output Settling 50% Logic to 90% Output Settling 50% Logic to 99.9% Output Settling ENABLE to Channel ON Time2 50% Logic to 90% Output Settling ENABLE to Channel OFF Time2 50% Logic to 90% Output Settling Channel Switching Transient (Glitch)3 DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Input Current Logic "0" Input Current DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal)4 -3 dB Bandwidth (Large Signal) 0.1 dB Bandwidth4, 5 Slew Rate Settling Time to 0.1% AD8184AR AD8184AR AD8184AR
Conditions Channel-to-Channel IN0 = +1 V, IN1 = -1 V A0, A1 = 0 or 1 IN0 = +1 V, -1 V or IN1 = -1 V, +1 V A0, A1 = 0 or 1 IN1 = +1 V, -1 V or IN1 = -1 V, +1 V All Inputs Are Grounded A0, A1 and ENABLE Inputs A0, A1 and ENABLE Inputs A0, A1, ENABLE = +4 V A0, A1, ENABLE = +0.4 V VIN = 50 mV rms, RL = 5 k VIN = 1 V rms, RL = 5 k VIN = 50 mV rms, RL = 5 k 2 V Step 2 V Step = 3.58 MHz, RL = 2 k f = 3.58 MHz, RL = 10 k f = 3.58 MHz, RL = 2 k f = 3.58 MHz, RL = 10 k = 5 MHz = 30 MHz = 5 MHz, RL = 30 = 30 MHz C = 10 MHz, VO = 2 V p-p, RL = 1 k VIN = 1 V TMIN to TMAX
5 10 15 12 22 25 2.0 10 2 550 105 60 600 700 135 75 750 15 0.2 0.01 0.2 0.01 -95 -78 -115 4.5 -74 0.982 2 5 0.6 2.5 5 1.0 2.4 1.6 1.6 3.3 3.2 30 28 10 3.2 0.8 200 3
ns ns ns ns ns mV V V nA A MHz MHz MHz V/s ns % % Degrees Degrees dB dB dB nV/Hz dBc V/V mV mV V/C mV A A nA/C M pF pF V V mA M pF V dB dB mA mA mA mA C
DISTORTION/NOISE PERFORMANCE Differential Gain Differential Phase All Hostile Crosstalk6 OFF Isolation7 Voltage Noise Total Harmonic Distortion AD8184AR AD8184AR
0.02 0.02
DC/TRANSFER CHARACTERISTICS Voltage Gain8 Input Offset Voltage Input Offset Voltage Drift Input Offset Voltage Matching Input Bias Current Input Bias Current Drift INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Current Output Resistance Output Capacitance POWER SUPPLY Operating Range Power Supply Rejection Ratio Power Supply Rejection Ratio Quiescent Current
8 15 3 7.5 9.5
Channel-to-Channel TMIN to TMAX
Channel Enabled (R Package) Channel Disabled (R Package)
VIN = 4 V, RL = 2 k9 Enabled Disabled Disabled (R Package)
3.15
33
+PSRR -PSRR
+VS = +4.5 V to +5.5 V, -VS = -5 V -VS = -4.5 V to -5.5 V, +VS = +5 V Enabled TMIN to TMAX Disabled TMIN to TMAX
4 54 51
6 57 54 4.4 2.1 5.2 5.7 2.9 2.9 +85
OPERATING TEMPERATURE RANGE
-40
-2-
REV. 0
AD8184
NOTES 1 ENABLE pin is grounded. IN0 and IN2 = +1 V dc, IN1 and IN3 = -1 V dc. A0 is driven with a 0 V to +5 V pulse, A1 is grounded. Measure transition time from 50% of the A0 input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (-1 V), or vice versa. All inputs are measured in a similar manner using A0 and A1 to select the channels. 2 ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). The state of the A0 and A1 pins determines which input is activated (refer to Table I). Set IN0 and IN2 = +1 V dc, IN1 and IN3 = -1 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 4, tOFF is the disable time, tON is the enable time. 3 All inputs are grounded. A0 input is driven with 0 V to +5 V pulse, A1 is grounded. The output is monitored. Speeding the edges of the A0 pulse increases the glitch magnitude due to coupling via the ground plane. Removing the A0 and A1 terminations will lower the glitch, as does increasing R L. 4 Decreasing RL slightly lowers the bandwidth. Increasing CL significantly lowers the bandwidth (see Figure 18). 5 A resistor (R S) placed in series with the multiplexer inputs serves to optimize 0.1 dB flatness, but is not required (see Figure 19.) 6 Select an input that is not being driven (i.e., A0 and A1 are logic 0, IN0 is selected); drive all other inputs with V IN = 0.707 V rms and monitor the output at = 5 and 30 MHz. RL = 2 k (see Figure 12). 7 Multiplexer is disabled (i.e., ENABLE = logic 1) and all inputs are driven simultaneously with V IN = 0.446 V rms. Output is monitored at = 5 and 30 MHz. R L = 30 to simulate RON of one enabled multiplexer within a system (see Figure 13). In this mode the output impedance is very high (typ 10 M), and the signal couples across the package; the load impedance determines the crosstalk. 8 Voltage gain decreases for lower values of R L. The resistive divider formed by the multiplexers enables output resistance (28 ) and RL causes a gain that increases as R Ldecreases (i.e., the voltage gain is approximately 0.97 V/V [3% gain error] for R L = 1 k). 9 Larger values of RL provide wider output voltage swings, as well as better gain accuracy. See Note 8. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 14-pin plastic package: JA = 75C/Watt 14-pin SOIC package: JA = 120C/Watt, where PD = (TJ -TA)/JA.
MAXIMUM POWER DISSIPATION - Watts
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V Internal Power Dissipation2 AD8184 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts AD8184 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . Observe Power Derating Curves Storage Temperature Range N & R Package . . . . . . . . . . . . . . . . . . . . . -65C to +125C Lead Temperature Range (Soldering 10 sec) . . . . . . . +300C
While the AD8184 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 2.
2.5 TJ = +150C
2.0 14-PIN DIP PACKAGE
1.5
14-PIN SOIC 1.0
ORDERING GUIDE
Model AD8184AN AD8184AR AD8184AR-REEL AD8184-EB Temperature Range -40C to +85C -40C to +85C -40C to +85C Evaluation Board Package Description Package Option
14-Lead Plastic DIP N-14 14-Lead Narrow SOIC R-14 Reel 14-Lead SOIC R-14 For AD8184R
0.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C
80 90
Figure 2. Maximum Power Dissipation vs. Temperature
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8184 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8184 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-3-
AD8184-Typical Performance Curves
5
DUT OUT 500mV/DIV
4 3
A0 PULSE 0 TO 5V
VIN = 50mVrms RL = 5k RS = 0
NORMALIZED OUTPUT - dB
2 1 0 -1 -2 -3 -4
1V OUTPUT
-1V
5ns/DIV
-5 1M
10M 100M FREQUENCY - Hz
1G
Figure 3 Channel Switching Characteristics
Figure 6. Small Signal Frequency Response
0.5 0.4
NORMALIZED FLATNESS - dB
0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4
VIN = 50mVrms RL = 5k RS = 0
+1V DUT OUT 800mV/DIV -1V +1V
PULSE 0 TO 5V
-1V
tOFF
tON
10ns/DIV
-0.5 1M 10M 100M FREQUENCY - Hz 1G
Figure 4. Enable and Disable Switching Characteristics
Figure 7. Gain Flatness vs. Frequency
3 RL = 5k 0
OUTPUT SWITCHING A0 25mV/DIV
VIN = 1.0Vrms
-3 -6
OUTPUT - dBV
VIN = 0.5Vrms
-9 -12 -15 -18 VIN = 125mVrms VIN = 0.25Vrms
OUTPUT SWITCHING A1
A0 and A1 PULSE 0 TO +5V
-21 -24 VIN = 62.5mVrms
25ns/DIV
-27 1M 10M 100M FREQUENCY - Hz 1G
Figure 5. Channel Switching Transient (Glitch)
Figure 8. Large Signal Frequency Response
-4-
REV. 0
AD8184
-10
OUTPUT @ 50mV
-20 -30
CROSSTALK - dB
50
1 3
VIN = 0.707Vrms RL = 2k
-40
VIN
50 50
5 7
10
OUTPUT 2k
OUTPUT @ 100mV 50mV/DIV
-50 -60 -70 -80 -90
AD8184
INPUT
-100
5ns/DIV
-110 100k
1M
10M FREQUENCY - Hz
100M
1G
Figure 9. Small Signal Transient Response
Figure 12. All-Hostile Crosstalk vs. Frequency
-30 -40 -50
OFF ISOLATION - dB OUTPUT = + 2V - 2V/DIV
VIN = 0.446 Vrms RL = 30
1 3 50 VIN 50 7 5 10 OUTPUT 30
= LOGIC 1
-60 -70 -80 -90 -100 -110 -120
OUTPUT = + 1V -
AD8184
INPUT
10ns/DIV
-130 100k 1M 10M FREQUENCY - Hz 100M 1G
Figure 10. Large Signal Transient Response
Figure 13. "OFF" Isolation vs. Frequency
VOLTAGE NOISE - nV/ Hz
0.05 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 0.05 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05
DIFFERENTIAL GAIN - %
RL = 2k NTSC
100
1
2
3
4
5
6
7
8
9
10
11
10
DIFFERENTIAL PHASE - Deg
1
10
100
1k
1
2
3
4
5
6
7
8
9
10
11
10k 100k FREQUENCY - Hz
1M
10M 30M
Figure 11. Differential Gain and Phase Error
Figure 14. Voltage Noise vs. Frequency
REV. 0
-5-
AD8184-Typical Performance Curves
0 -10
HARMONIC DISTORTION - dBc
0.8 VOUT = 2V p-p RL = 1k NORMALIZED FLATNESS - dB 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 1M 100pF 33pF VIN = 50mVrms RL = 5k RS = 0 33pF 100pF 10pF 0pF
1 0 NORMALIZED OUTPUT - dB -1 -2 -3 -4 -5 -6 -7 -8 10M 100M FREQUENCY - Hz -9 1G
-20 -30 -40 -50 -60 2ND HARMONIC -70 -80 -90 3RD HARMONIC
-100 100k
1M
10M FREQUENCY - Hz
100M
Figure 15. Harmonic Distortion vs. Frequency
Figure 18. Frequency Response vs. Capacitive Load
100M
150 140 130 120 110 ZIN 100 90 80 70 60 50 ZOUT (ENABLED) 40 30 20
0.8 0.7 ENABLED OUTPUT IMPEDANCE -
INPUT AND DISABLED OUTPUT IMPEDANCE
RS = 0 VIN = 50mVrms RL = 5k RS = 150 RS = 75 RS = 0 RS = 75
1 0
10M 1M
NORMALIZED FLATNESS - dB
0.5 0.4 0.3 0.2 0.1 0
-2 -3 -4 -5 -6 -7
100k 10k 1k ZOUT (DISABLED)
100 10 100
-0.1 -0.2 1M
RS = 150
-8 -9 1G
1k
10k
100k 1M FREQUENCY - Hz
10M
100M
10 1G
10M 100M FREQUENCY - Hz
Figure 16. Output & Input Impedance vs. Frequency
Figure 19. Frequency Response vs. Input Series Resistance
0 -10 -20 -30
5 4 3
OUTPUT VOLTAGE - Volts
2 1 0 -1 -2 -3
PSSR - dB
+PSRR -40 -PSRR -50 -60 -70 -80 0.03M
-4 -5 -5
0.01M
1M 10M FREQUENCY - Hz
100M
500M
-4
-3
-2 -1 0 1 2 INPUT VOLTAGE - Volts
3
4
5
Figure 17. Power Supply Rejection vs. Frequency
Figure 20. Output Voltage vs. Input Voltage, RL = 2 k
-6-
REV. 0
NORMALIZED OUTPUT - dB
0.6
-1
AD8184
THEORY OF OPERATION
The AD8184 video multiplexer is designed for fast switching (10 ns) and wide bandwidth (> 700 MHz). This performance is attained with low power dissipation (4.4 mA, enabled) through the use of proprietary circuit techniques and a dielectricallyisolated complementary bipolar process. This device has a fast disable function that allows the outputs of several muxes to be wired in parallel to form a larger mux with little degradation in switching time. The low disabled output capacitance (3.2 pF) helps to preserve the system bandwidth in larger matrices. Unlike earlier CMOS switches, the switched open-loop buffer architecture of the AD8184 provides a unidirectional signal path with minimal switching glitches and constant, low input capacitance. Since the input impedance of these muxes is nearly independent of the load impedance and the state of the mux, the frequency response of the ON channels in a large switch matrix is not affected by fanout. Figure 21 shows a block diagram and simplified schematic of the AD8184, which contains four switched buffers (S0-S3) that share a common output. The decoder logic translates TTLcompatible logic inputs (A0, A1 and ENABLE) to internal, differential ECL levels for fast, low-glitch switching. The A0 (LSB) and A1 (MSB) control inputs constitute a two-bit binary word that determines which of the four buffers is enabled, unless the ENABLE input is HIGH, in which case all buffers are disabled and the output is switched to a high impedance state. Each open-loop buffer is implemented as a complementary emitter follower that provides high input impedance, symmetric slew rate and load drive, and high output-to-input isolation due to its 2 current gain. The selected buffer is biased ON by fast switched current sources that allow the buffer to turn on quickly. Dedicated flatness circuits, combined with the open-loop architecture of the AD8184, keep peaking low (typically < 0.5 dB) when driving high capacitive loads, without the need for external
series resistors at the input or output. If better flatness response is desired, an input series resistance (RS) may be used (refer to Figure 19), although this will increase crosstalk. The dc gain of the AD8184 is almost independent of load for RL > 10 k. For heavier loads, the dc gain is approximately that of the voltage divider formed by the output impedance of the mux (typically 28 and RL). High speed disable clamp circuits (not shown) at the bases of Q3 and Q4 allow the buffers to turn off quickly and cleanly without dissipating much power once off. Moreover, these clamps shunt displacement currents flowing through the junction capacitances of Q1 and Q2 away from the bases of Q3 and Q4 and to ac ground through low impedances. The two-pole high-pass frequency response of the T switch formed by these clamps is a significant improvement over the one-pole high pass response of a simple series CMOS switch. As a result, board and package parasitics, especially stray capacitance between inputs and outputs, may limit the achievable crosstalk and off isolation.
LAYOUT CONSIDERATIONS:
Realizing the high speed performance attainable with the AD8184 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. Wire wrap boards, prototype boards and sockets are not recommended because of their high parasitic inductance and capacitance. Instead, surface-mount components should be directly soldered to a printed circuit board (PCB). The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. To reduce stray capacitance the ground plane should be removed from the area near input and output pins.
AD8184
I1 Q3
IN0
1
Q1 I2 S0
Q2 Q4
14 VCC
I1 Q3
DECODER
GND
2
13 A0
IN1
3
Q1 I2 S1
Q2 Q4
12 A1
GND
4
11
I1 Q3
IN2
5
Q1 I2 S2
Q2 Q4
10
OUT
GND
6
9
NC
I1 Q3
IN3
7
Q1 I2 S3
Q2 Q4
8
VEE
NC = NO CONNECT
Figure 21. Block Diagram and Simplified Schematic of the AD8184 Multiplexer
REV. 0
-7-
AD8184
Chip capacitors should be used for supply bypassing. One end of the capacitor should be connected to the ground plane and the other within 1/4 inch of each power pin. An additional large (4.7 F-10 F) tantalum capacitor should be connected in parallel with each of the smaller capacitors for low impedance supply bypassing over a broad range of frequencies. Signal traces should be as short as possible. Stripline or microstrip techniques should be used for long (longer than about 1 inch) signal traces. These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end using surface mount components. Careful layout is imperative to minimize crosstalk. Guards (ground or supply traces) must be run between all signal traces to limit direct capacitive coupling. Input and output signal lines should fan out away from the mux as much as possible. If multiple signal layers are available, a buried stripline structure having ground plane above, below and between signal traces will have the best crosstalk performance. Return currents flowing through termination resistors can also increase crosstalk if these currents flow in sections of the finiteimpedance ground circuit shared between more than one input or output. Minimizing the inductance and resistance of the ground plane can reduce this effect, but further care should be taken in positioning the terminations. Terminating cables directly at the connectors will minimize the return current flowing on the board, but the signal trace between the connector and the mux will look like an open stub and will degrade the frequency response. Moving the termination resistors close to the input pins will improve the frequency response, but the terminations from neighboring inputs should not have a common ground return.
APPLICATIONS A Buffered 4-to-1 Multiplexer
In applications where the output of a multiplexer must drive a back-terminated 75 line (RL = 75 + 75 ), it is necessary to buffer the output of the AD8184. In the example in Figure 22, this is accomplished using the AD8009 high speed current feedback op amp. The amplifier is configured with a gain of 2 to compensate for the signal halving due to termination at the multiplexer input. This gives the overall circuit a gain of unity. If lower speed can be tolerated, a number of other amplifiers can replace the AD8009 op amp in the above circuit. In general there is a trade-off between bandwidth and power consumption. Table II summarizes the bandwidth and power consumption characteristics of these op amps.
Table II. Amplifier Options for Multiplexer Buffering
Op Amp Comments AD8009 Highest Bandwidth, (G = +2) = 700 MHz, ISY = 14 mA AD8001 Lower Power Consumption, Bandwidth (G = +2) = 440 MHz, ISY = 5 mA AD8011 Lower Power Consumption, Bandwidth (G = +2) = 210 MHz, ISY = 1 mA AD8079 Fixed Gain Dual Amplifier (2 or 2.2), Bandwidth = 260 MHz, ISY = 5 mA Per Amp AD8005 Lowest Power Consumption, Bandwidth (G = +2) = 170 MHz, ISY = 400 A
A0
A1
10F
AD8184
IN0 75 2 GND IN1 75 4 GND IN2 75 6 GND +1 IN3 75 7 -VS 8 NC 9 5 +1
DECODER
1 +1
+VS 14 13 +1 12
0.1F
+VS +VS
3
10F 11 10 AD8009 75 -VS 0.1F -VS 10F 681 681 0.1F 0.1F VOUT
10F
Figure 22. A Buffered 4-to-1 Multiplexer
-8-
REV. 0
AD8184
Color Document Scanner A4 4 Crosspoint Switch
Figure 23 shows a block diagram of a Color Document Scanner. Charge Coupled Devices (CCDs) find widespread use in scanner applications. A monochrome CCD delivers a serial stream of voltages levels, each level being proportional to the light shining on that cell. In the case of the color image scanner shown, there are three output streams, representing red, green and blue. Interlaced with the stream of voltage levels is a voltage representing the reset level (or black level) of each cell. A Correlated Double Sampler (CDS) subtracts these two voltages from each other in order to eliminate the relatively large offsets common with CCDs.
CONTROL & TIMING
While large crosspoint arrays are best constructed using highly integrated devices such as the AD8116, 16 x 16 crosspoint switch, smaller or irregular sized arrays can be constructed using 4-to-1 multiplexers such as the AD8184. The circuit below shows a 4 x 4 array, constructed using the AD8184 and buffered using the AD8079, a dual, fixed gain of 2 or 2.2, video amplifier.
AD8184
4
1/2 AD8079* OUT0
IN0-IN3
OUT
750
750
AD8184
R G CCD B A0 A1 ENABLE CDS CDS CDS REFERENCE 10F 0.1F OUT
1/2 AD8079* OUT1
AD9220
10/12-BIT 10MSPS A/D CONVERTER VINA VINB VREF SENSE IN0-3
4
IN0-IN3
OUT
4
750
750
AD8184
AD8184
4
1/2 AD8079* OUT2
IN0-IN3
OUT
Figure 23. Color Document Scanner
750
750
The next step in the data acquisition process involves digitizing the three signal streams. Assuming that the analog-to-digital converter chosen has a fast enough sample rate, multiplexing the three streams into a single ADC is generally more economical than using one ADC per channel. In the example shown, we use the AD8184 as the multiplexer. Because of its high bandwidth, the AD8184 is capable of driving the switched capacitor input stage of the AD9220 without additional buffering. In addition to having the required bandwidth, it is necessary to consider the settling time of the multiplexer. In this case, the ADC has a sample rate of 10 MHz, which corresponds to a sampling period of 100 ns. Typically, one phase of the sampling clock is used for conversion (i.e., all levels are held steady) and the other is used for switching and settling to the next channel. Assuming a 50% duty cycle, the signal chain must settle within 50 ns. With a settling time to 0.1% of 15 ns, the multiplexer easily satisfies this criterion. In the example shown, the fourth (spare) channel of the AD8184 is used to measure a reference voltage. This voltage would probably be measured less frequently than the R, G and B signals. Multiplexing a reference voltage offers the advantage that any temperature drift effects caused by the multiplexer will equally impact the reference voltage and the to-be-measured signals. If the fourth channel is unused, it is good design practice to permanently tie it to ground.
AD8184
4
1/2 AD8079* OUT3
IN0-IN3
OUT
750
750
*AD8079 IS A DUAL, FIXED GAIN OF 2 AMPLIFIER
Figure 24. 4 x 4 Crosspoint Switch
REV. 0
-9-
AD8184
C4 10F +VS
AD8184
IN0 R4 49.9 1 +1 2 GND 3 R3 49.9 4 GND 5 R2 49.9 6 GND +1 IN3 R1 49.9 7 -VS 8 +1 +1
DECODER
C3 0.1F +VS 14 13 12 11 10 NC 9 R8 4.99k C2 0.1F R7 49.9 OUT (SCOPE PROBE ADAPTER) R5 49.9 A0
IN1
A1 R6 49.9
IN2
-VS
C1 10F
Figure 25. AD8184AR Evaluation Board
EVALUATION BOARD
An evaluation board is available for the AD8184. It has been carefully laid out and tested to demonstrate the specified high speed performance of the devices. Figure 25 shows the schematic of the evaluation board. For ordering information, please refer to the Ordering Guide. Figure 26 shows the silkscreen of the component side and Figure 28 shows the silkscreen of the solder side. Figures 27 and 29 show the layout of the component side and solder side respectively. The evaluation board is provided with 49.9 termination resistors on all inputs. This is to allow the performance to be evaluated at very high frequencies where 50 termination is most popular. To use the evaluation board in video applications, the termination resistors should be replaced with 75 resistors. The FR4 board type has the following stripline dimensions: 60-mil width, 12-mil gap between center conductor and outside ground plane "island" and 62-mil board thickness. The multiplexer output is loaded with a 4.99 k resistor. For connection to external instruments, an oscilloscope probe adapter is provided. This allows direct connection of an FET
probe to the board. For verification of data sheet specifications, use of an FET probe is recommended because of its low input capacitance. The probe adapter used on the board has the same footprint as SMA, SMB and SMC type connectors, allowing easy replacement if necessary. The side-launched SMA connectors on the analog and digital inputs can also be replaced by top-mount SMA, SMB or SMC type connectors. When using top-mount connectors, the stripline on the outside 1/8" of the board edge should be removed with an X-acto blade as this unused stripline acts as an open stub, which could degrade the small-signal frequency response of the multiplexer. Input termination resistor placement on the evaluation board is critical to reducing crosstalk. Each termination resistor is oriented so that the ground return currents flow counterclockwise to the ground plane "island." Although the direction of this ground current flow is arbitrary, it is important that no two input or output termination resistors share a connection to the same ground "island."
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AD8184
Figure 26. Component Side Silkscreen
Figure 28. Solder Side Silkscreen
Figure 27. Board Layout (Component Side)
Figure 29. Board Layout (Solder Side)
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AD8184
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP (N-14)
0.795 (20.19) 0.725 (18.42)
14 1 8 7
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC
SEATING PLANE
0.015 (0.381) 0.008 (0.204)
14-Lead SOIC (R-14)
0.3444 (8.75) 0.3367 (8.55)
14 1 8 7
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
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PRINTED IN U.S.A.
C3036-10-4/97

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